Design of PD and High Performance VCO for PLL with 45 nm CMOS Technology
In this paper, the authors describe design aspects for low power and high performance phase locked loop using 45nm process technology. The paper contains CMOS design of PFD, charge pump and loop filter, VCO. The design is simulated with 45nm CMOS technology. The software Microwind 3.1 is used to allow the users to design and simulate an integrated circuit at physical description level. The main novelty related to the 45nm technology such as the high-k gate oxide, metal-gate and very low-k interconnect dielectric described.