Design of Power Optimization using C2H Hardware Accelerator and NIOS II Processor

Provided by: International Journal of Computer Science and Mobile Computing (IJCSMC)
Topic: Hardware
Format: PDF
The current trend in the silicon industry has been a move steadily towards Chip Multicore Processor (CMP) system to get better outputs. However, chip multicore processors have higher amount of soft errors, which result in degradation of the overall system reliability. Hence, the authors have been cautious of using CMP architectures for faster-reliable embedded real-time system applications that have high reliability levels. The major use of these processors also states the processor migration tendency. With new technology processor architectures, the older ones are to become vanished sooner. Present the power optimization and detailed reliability analysis of power optimization of single-core and multi-core based systems.

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