Design of Process Variation 3T1D-Based DRAM Using CADENCE

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Provided by: International Journal of Emerging Technology and Advanced Engineering (IJETAE)
Topic: Hardware
Format: PDF
In this paper, the authors deal with the design and analysis of 3T1D DRAM cell to develop process variation architectures using cadence tool. With continued technology scaling, process variations will be especially detrimental to Three-Transistor One Diode Dynamic Random Access Memory (3T1D DRAM) structures. A memory architecture using 3T1D DRAM cells using cadence tool wide process variations with different technology 0.6um ami, 0.40um tsmc, and 0.30um tsmc performance, making it a promising choice for 3T1D cell on-chip cache structures for next-generation microprocessors.
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