Design of Process Variation 4-bit 50MS/s SAR ADC in submicron CMOS Technology

Provided by: International Journal of Engineering and Innovative Technology (IJEIT)
Topic: Hardware
Format: PDF
In this paper, presents the design and analysis of SAR ADC to develop process variation architectures. Data convertor ADC SAR architecture simulate on 1V, for 4 bit resolution. Design simulate for process variations with different submicron technology. Performance of convertor making it a promising choice for SAR ADC data convertor on chip structures for next-generation emerge digital systems. Process variation is mainly caused by fluctuations in dopant concentrate ions and device channel dimensions. Paper contains logical design and simulation results of all design elements like comparator, DAC etc.

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