Design of Pulse Triggered FlipFlop for Low Power Applications
Most important challenge in modern VLSI design along with area and speed is the power consumption. Flip-flop is the basic element in digital system which plays very important role. In this paper, a low power pulse triggered flip-flop with feed through technique is proposed. The proposed design introduces a series pass transistor which helps in reducing discharging path. By performing post layout simulation of design based on 90nm technology using HSPICE at 500MHz/1.0V revel that the proposed design excels in performance indexes such as power, D-to-Q delay, EDP.