Design of Quaternary Adder for High Speed Applications

Provided by: International Journal of Pure and Applied Research in Engineering and Technology (IJPRET)
Topic: Hardware
Format: PDF
Routing has become the main contributor in many areas of design such as area, delay and power. Multiple Valued Logic (MVL) offers a means to reduce the routing since each wire in MVL can carry the twice as much information as single binary wire. Reducing this routing directly leads to the reduction of overall circuit area and power consumption. Rapid advancement in VLSI technology makes it possible to couple several binary inputs to form a multivalued input for faster processing.

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