Design of Quaternary Arithmetic Unit in Standard CMOS
The Multiple-Valued Logic (MVL) plays very important role in VLSI (Very-Large-Scale Integration) circuit design. The number of interconnections is reduced by using quaternary logic than binary logic. In this paper, the authors present the design of a prototype implementation and experimental results. Quaternary converter circuits are designed by using Down Literal Circuits (DLCs). Addition, subtraction and multiplication i.e. arithmetic operations in modulo-4 and in Galois field logic are design and simulation results are shown in this paper by using quaternary logic.