Provided by: The IJIRD
Date Added: Feb 2013
FFT is suitable for high speed environment because it provides the transfer of data at a very high speed. This paper is to design an FFT with the help of Matlab and Simulink along with System Generator (SysGen). Such tools take as their input a high-level representation of an application written in Matlab R2007a and generate RTL (Register Transfer Level) implementation for an FPGA. The RTL code is synthesized using Xilinx Project navigator Xilinx ISE 9.2i and simulated using ModelSim 5.8c simulator providing superior performance making it an increasingly preferred choice of many engineers today.