Design of Random Testing Circuit Based on Lfsr for the External Memory Interface

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Provided by: International Journal of Application or Innovation in Engineering & Management (IJAIEM)
Topic: Hardware
Format: PDF
In the design of a SOC system, random test is gradually becoming an application for IP cores verification. This paper proposes a new random testing circuit based on LFSR to test the integrated EMIF IP core with restricted random verification methods. With the pseudo-random numbers generated by LFSR which works as a pseudo-random number generator, the testing circuit converts the numbers into test vectors which meet the AHB protocol. The test results indicate this circuit achieves random testing of the EMIF IP core.
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