This paper presents implementation of 10x10 Reconfigurable Crossbar Switch (RCS) architecture for Dynamic Self-Reconfigurable BiNoC Architecture for Network On Chip. Its main purpose is to increase the performance, flexibility. This paper presents a VHDL based cycle accurate register transfer level model for evaluating the, Power and Area of reconfigurable crossbar switch in BiNoC architectures. The authors implemented a parameterized register transfer level design of Reconfigurable Crossbar Switch (RCS) architecture. The design is parameterized on size of packets, length and width of physical links, number, and depth of arbiters, and switching technique.