Design of Reconfigurable FFT Processor with Reduced Area and Power

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Provided by: IT Society of India (ITSI)
Topic: Hardware
Format: PDF
Fast Fourier Transform (FFT) is an efficient implementation of the Discrete Fourier Transform (DFT). The paper is to implement a reconfigurable FFT processor with reduced power and area in order to provide system designers and engineers with the flexibility to meet different system requirements. This paper proposes a low power and area efficient FFT architecture using Single Delay Feedback (SDF). The proposed methodology is based on radix factorization which is the main technique for achieving high energy efficiency with flexibility, followed by architecture parallelism.
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