International Journal of Advanced Research in Computer Engineering & Technology
Network-On-Chip (NOC) has been proposed as an attractive alternative to traditional dedicated wire to achieve high performance and modularity. Power and Area efficiency is the most important concern in NOC design. This paper introduces a novel unified buffer structure, called the Dynamic Reconfigure Virtual Channel Regulator, which dynamically allocates Virtual Channels (VC) and buffer resources according to network traffic conditions. It maximizes throughput by dispensing a variable number of VCs on demand. Dynamic Reconfigure Virtual Channels ability to provide similar performance with half the buffer size of a generic router is of paramount importance. This paper presents a VHDL based cycle accurate register transfer level model for evaluating the, Area of Dynamically self Reconfigurable BiNoC architectures.