Design of Reversible Fault Tolerent Decoder Using MOS Transistors
In this paper, the authors demonstrate the reversible logic synthesis for the n-to-2n decoder, where n are the fault tolerant Fredkin and Feynman double gates. Thus, the entire scheme inherently becomes fault tolerant. Algorithm for designing the generalized decoder has been presented. In addition, several lower bounds on the number of constant inputs, garbage outputs and quantum cost of the reversible fault tolerant decoder have been proposed. Transistor simulation of the proposed design is shown in microwind 3.0 version where power area and delay are calculated.
Provided by: International Journal of Computer Science and Information Technologies Topic: Hardware Date Added: May 2014 Format: PDF