Design of Sample & Hold Circuit

Provided by: International Journal of Scientific and Research Publication (IJSRP)
Topic: Hardware
Format: PDF
In this paper, the authors describe the design of a high-speed CMOS Sample and Hold circuit in front of an Analog to Digital Converter (ADC). Sample and Hold (S/H) circuit employs linear source follower buffer at input and output. Synopsys cosmos SE software tool has been used for schematic design, H-spice for Simulation and Cscope for waveform performance. Complete S/H circuit has designed with tsmc035 (Taiwan semiconductor manufacturing corporation) technology, with 2.5V power supply. Power consumption of 5 mW for 8 MHz at 53 MS/s.

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