Design of Second-Order Sigma-Delta Modulator Using CMOS Technology
The use of over-sampling sigma-delta modulators in the integration of high-resolution analog-to-digital converters has shown promise for overcoming the analog component limitations inherent in modern VLSI technologies. Sigma delta modulators employ coarse quantization enclosed in one or more feedback loops. As a part of wider project sigma-delta modulator was designed. It represents an A/D part of a power meter IC. Requirements imposed were: SNDR and dynamic range greater than 50 dB for maximum input swing of 250 mV differential at 50 Hz. Over-sampling ratio is 128 with clock frequency of 524288 Hz which gives bandwidth of 2048 Hz. Circuit is designed in 3.3 V supply standard CMOS 0.35 um technology.