International Journal of Innovative Science Engineering and Technology (IJISET)
The storage elements are major power consuming component in VLSI system. The power reduction of storage element leads to reduction of global power consumption of VLSI system. In this paper, a proposed Single Edge Triggered (SET) and a proposed Double Edge Triggered (DET) logic module flip-flops are modeled and implemented by using TannerEDA. The DET offers a power reduction up to 13.34% compared to the conventional flip-flops. A new proposed SET offer the power consumption up to 14.28% compared to conventional flip-flops and 9.34% power improvement compare with proposed DET.