Design of the ARM VFP11 Divide and Square Root Synthesisable Macrocell

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Provided by: Cardiff University
Topic: Hardware
Format: PDF
In this paper, the authors present the detailed design of the ARM VFP11 Divide and Square Root synthesisable macrocell. The macrocell was designed using the minimum-redundancy radix-4 SRT digit recurrence algorithm, and this paper describes a novel acceleration technique employed to achieve the required processor clock frequency of up to 750MHz in 90nm CMOS. Logical effort theory is used to provide a delay analysis of the unit, which demonstrates the balanced nature of the two critical paths therein.
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