Provided by: International Journal of Emerging Technology and Advanced Engineering (IJETAE)
Date Added: Jan 2015
In this paper, the authors target the design and the implementation of a low power PCI master operation having error checking and correction feature. Low Density Parity Check (LDPC) technique has been used for error checking and correction in the proposed PCI master architecture. Input data is 7-bit which will be encoded to 15-bit at LDPC encoder block and later which will be decoded to 7-bit at output of LDPC decoder block. Design frequency is of 33MHz. This proposed architecture is having a capability of detecting single bit error and it will not affect the data transfer i.e., the original data will be same although error is introduced in the data transfer.