Design of Vedic Multiplier for Digital Signal Processing Applications

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Provided by: International Journal of Engineering Trends and Technology
Topic: Hardware
Format: PDF
Multiplier is one of the most important parts in any processor speed which improves the speed of the operation like in special application processors like Digital Signal Processors (DSPs). To increase the speed of operation, the authors should take care of the precision previously, they used the floating point multipliers which were consume more silicon area and take more clock frequency than fixed point (Qformat) multipliers. Now, they propose a method which is faster multiplication technique by using Vedic mathematics formula Urdhava Tiryakbhyam method which means vertically and cross wire.
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