Design Space Exploration for 3D-Stacked DRAMs

Provided by: edaa
Topic: Storage
Format: PDF
3D integration based on TSV (Through Silicon Via) technology enables stacking of multiple memory layers and has the advantage of higher bandwidth at lower energy consumption for the memory interface. As in mobile applications energy efficiency is key, 3D integration is especially here a strategic technology. In this paper, the authors focus on the design space exploration of 3D-stacked DRAMs with respect to performance, energy and area efficiency for densities from 256Mbit to 4Gbit per 3DDRAM channel. They investigate four different technology nodes from 75nm down to 45nm and show the optimal design point for the currently most common commodity DRAM density of 1Gbit.

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