Design Space Exploration of Instruction Schedulers for Out-of-Order Soft Processors

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Provided by: University of Toledo
Topic: Data Centers
Format: PDF
In this paper, the authors explore instruction scheduler designs for single-issue, out-of-order soft processors targeting irregular workloads. It shows the effect of scheduler size, scheduling policy and back-to-back scheduling on performance, area, and frequency. It is shown that for a modern, high-end FPGA (Altera Stratix III) the best performance is achieved by a small, 4-entry instruction scheduler with an age-based instruction selection policy and back-to-back scheduling. A combined scheduler and register renamer is shown to operate at 303MHz.
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