Design Space Exploration Tools for the ByoRISC Configurable Processor Family

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Provided by: Aristotle University of Thessaloniki
Topic: Hardware
Format: PDF
In this paper, the ByoRISC (\"Build your own RISC\") configurable Application-Specific Instruction-set Processor (ASIP) family is presented. ByoRISCs, as vendor-independent cores, provide extensive architectural parameters over a baseline processor, which can be customized by Application-Specific Hardware Extensions (ASHEs). Such extensions realize Multi-Input Multi-Output (MIMO) custom instructions with local state and load/store accesses to the data memory. ByoRISCs incorporate a true multi-port register file, zero-overhead custom instruction decoding, and scalable data forwarding mechanisms. Given these design decisions, ByoRISCs provide a unique combination of features that allow their use as architectural testbeds and the seamless and rapid development of new high-performance ASIPs.
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