International Journal of Computer Applications
Reduction of power dissipation is one of the most important challenges in VLSI circuit design. Due to scaling, sub-threshold leakage current plays a dominant role in total power dissipation. This paper illustrates application of power saving SVL technique on 2:1 NAND MUX architecture. This application offers significant reduction in leakage power and leakage current viz-a-viz previous techniques. Self-controllable Voltage Level (SVL) circuit technique drastically reduces stand by leakage power and leakage current of CMOS logic circuits.