Georgia Institute of Technology
3D integration is a promising new technology for tightly integrating multiple active silicon layers into a single chip stack. Both the integration of heterogeneous tiers and the partitioning of functional units across tiers leads to significant improvements in functionality, area, performance, and power consumption. Managing the complexity of 3D design is a significant challenge that will require a System-on-Chip (SoC) approach, but the application of SoC design to 3D necessitates extensions to current test methodology. In this paper, the authors propose extending test wrappers, a popular SoC DFT technique, into the third dimension.