Designing a Novel Power Efficient D- Flip-Flop Using Forced Stack Technique
In integrated circuits a gargantuan portion of on-chip power is expended by clocking systems, which comprises of timing elements such as flip-flops, latches and clock distribution network. These elements absorb approximately 30% to 60% of the total power dissipation in the system. In order to design high performance and power efficient circuits a scrupulous approach should be adopted to reduce the power consumed by flip-flops and latches. In this paper, various power efficient flip-flops with low power clock distribution network are examined.