Designing and Simulating a New Full Adder with Low Power Consumption
A full adder circuit, regarding its ability to operate the elementary arithmetic, i.e. addition, subtraction, multiplication and division, is considered as one the most important and applicable parts of digital processors in designing integrated circuits. Hence, the present paper tries to introduce a new full adder cell by the use of carbon nano-tube transistors technology for achieving a circuit with optimal performance and low power consumption. The proposed design consists of 12 CNTFET transistors which have been connected through the passing transistor logic.