Designing and Synthesizing a Wallace Tree Multiplier for High Speed Performance

Provided by: IJAIM
Topic: Hardware
Format: PDF
In this paper, the authors deal with design and synthesis of 8x8 Wallace Tree Multiplier (WTM). Multipliers form the heart of DSP operation and determine the performance of general-purpose microprocessors and other devices where multipliers are highly involved. However, addition is a fundamental operation of multiplier and the question is how the addition operation is performed in order to improve the speed of the multiplier. The paper proposed a new algorithm for Wallace Tree Multiplier (WTM) as it is an efficient hardware implementation of a circuit that multiplies two integers.

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