Designing Energy-Efficient Low-Diameter On-Chip Networks with Equalized Interconnects

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Provided by: Massachusetts Institute of Technology
Topic: Hardware
Format: PDF
In a power and area constrained multicore system, the on-chip communication network needs to be carefully designed to maximize the system performance and programmer productivity while minimizing energy and area. In this paper, the authors explore the design of energy-efficient low-diameter networks (flattened butterfly and Clos) using equalized on-chip interconnects. These low-diameter networks are attractive as they can potentially provide uniformly high throughput and low latency across various traffic patterns, but require efficient global communication channels.
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