Designing Heterogeneous ECU Networks via Compact Architecture Encoding and Hybrid Timing Analysis
In this paper, a design method for automotive architectures is proposed. The two main technical contributions are a novel hardware/ software architecture encoding that unifies a number of design steps, i.e., resource allocation, process binding, message routing, scheduling, and parameter estimation for the processor and bus schedulers and a hybrid scheme that allows different timing analysis techniques to be applied to different bus protocols (viz., CAN and FlexRay) within the same architecture in order to derive global performance estimates such as end-to-end delays of messages. The use of the compact encoding technique substantially reduces the underlying search space, and the hybrid timing analysis scheme allows the combination of known timing analysis techniques from the real-time systems domain.
Provided by: Association for Computing Machinery Topic: Hardware Date Added: Jul 2009 Format: PDF