Designing of High Speed Wallace Tree Multiplier Using SKS Adder

Power dissipation of integrated circuits is a major concern for VLSI circuit designers. A Wallace tree multiplier is an improved version of tree based multiplier architecture. It uses carry save addition algorithm to reduce the latency. This paper aims at additional reduction of latency and power consumption of the Wallace tree multiplier. Sparse Kogge-Stone adder is used in the proposed architecture is 20.4% faster than the previous skalsky adder. The simulations have been carried out using the simulator tool, synthesis by the Xilinx tool.

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