International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (IJAREEIE)
One of the primary goals of computer architects is to design computers that are more cost-effective than their processors. In this paper, the authors analyze the processor designed in this project was based on the MIPS R2000. The objective of the design is to run all Instructions in one cycle. It uses the separate harvard architecture, it increase the speed of processor. Previews RISK MIPS pipeline design consists 3stage pipeline design, but MIPS R2000 consists 5stage design. MIPS R2000 modules are implemented by pipeline and simulated successfully on Xilinx ise.