Designing Of Pipelined Architecture of Arithmetic Core and Analysis of Area and Timing Performance

In this paper, the authors proposed a designing of pipelined architecture of arithmetic core and analysis of area and timing performance of that arithmetic core consisting of fixed point as well as floating point arithmetic cores. The basic concept behind designing such a core is to optimally utilize the algorithms of fixed point as well as floating point arithmetic operations, i.e., addition, subtraction division and multiplication and to enhance the operational speed of these calculations along with comparing a better technique out of fixed and floating point techniques to choose one of them for implementing in future.

Provided by: Iosrjournals Topic: Hardware Date Added: Jun 2014 Format: PDF

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