Designing One-Bit Full-Adder/Subtractor Based on Multiplexer and LUT's Architecture on FPGA

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Provided by: AICIT
Topic: Hardware
Format: PDF
In this paper, the authors present new methods with the purpose to optimally implement and speed up one bit Full-Adder/Subtractor (FA/S). This optimal implementation helps the FA/S to use less resource on Field-Program able-Gate-Array (FPGA) than traditional FA/S. Based on Look-Up-Table (LUT)'s structures and properties shown by Xilinx and Altera company, FA/S operation, and also recent innovation in optimal multiplexer. In such optimal designs and implement proposed, LUT is divided into smaller LUT's, which can function as a multiplexer, a memory or a comparator, to increase the speed of FA/S, reduce the area occupied on FPGA, and use the resource appropriately.
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