Designing Ripple Carry Adder Using a New Design of the CMOS Full-Adders
In this paper, the authors present a method to designing ripple carry adder using CMOS full-adders for energy-efficient arithmetic applications. They present two high-speed and low-power full-adder cells de-signed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced Power-Delay Product (PDP). They carried out a comparison against other full-adders reported as having a low PDP, in terms of speed, power consumption and area. All the full-adders were designed with a 0.18 um CMOS technology, and were tested using a comprehensive test bench that allowed to measure the current taken from the full-adder inputs, besides the current provided from the power-supply.