University of Rome
Networks-on-Chip (NoC) have been suggested to cope with the issues caused by continuous scaling of transistor dimensions. To date, a large number of suggestions have been made for the different aspects of development and operation of large Network-on-Chip (NoC), ranging from bit transmission to the abstract management of such systems. Modeling environments have also been presented to verify and evaluate the overall system performance. Their pros and cons are discussed to motivate the need for the developed simulator that is described in this paper. Two more sections cover the use of the simulator in a design flow for Network-on-Chips (NoCs) and which investigations are intended to be done with it in the future.