Provided by: IDOSI
Date Added: Feb 2013
A 2-digit higher radix Analog-to-Digital Converter (ADC) circuit consisting of a combination of a pipelined ADC and a set of cascaded current comparator cell has been proposed. The ADC generates multi-valued logic outputs rather than the conventional binary output system. The design is implemented using 0.25 um CMOS process. The performance analysis of the design shows desirable performance parameters in terms of response and low power consumption. The ADC design is suitable for the needs of mixed-signal integrated circuit design and can be implemented as a conversion circuit for systems based on multiple valued logic design.