Development of Verification Environment for AXI Bus Using SystemVerilog

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Provided by: Engineering and Technology Publishing
Topic: Hardware
Format: PDF
System-on-Chip (SoC) design has become more and more complexly. How to verify a design effectively has become a serious challenge. In this paper, how to build up the effective verification environment of AXI using system Verilog is introduced. Firstly, the Design Under Verify (DUV) AXI bus is introduced. Then a comprehensive analysis of the verification plan has been made according to the protocol. The proposed integrated verification environment with Functional coverage, score-boarding, assertions and constrained random vectors generation is implemented.
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