DEW: A Fast Level 1 Cache Simulation Approach for Embedded Processors with FIFO Replacement Policy

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Provided by: edaa
Topic: Hardware
Format: PDF
Increasing the speed of cache simulation to obtain hit/miss rates enables performance estimation, cache exploration for embedded systems and energy estimation. Previously, such simulations, particularly exact approaches, have been exclusively for caches which utilize the Least Recently Used (LRU) replacement policy. In this paper, the authors propose a new, fast and exact cache simulation method for the First In First Out (FIFO) replacement policy. This method, called DEW, is able to simulate multiple level 1 cache configurations (different set sizes, associativities, and block sizes) with FIFO replacement policy.
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