DfT for the Reuse of Networks-on-Chip as Test Access Mechanism
In this paper, the authors present new DfT modules required to use Network-on-Chips (NoCs) as test access mechanism. They demonstrate that the proposed DfT modules can be also implemented on top of low cost Network-on-Chip (NoC), i.e. networks without complex services. The DfT modules, which consist of test wrappers and test pin interfaces, are designed such that both the tester and CUTs transport test data unaware of the network. They analyze the DfT modules in terms of silicon area and test time, considering different network and test configurations.