International Journal of Computer Applications
In the present paper, mainly power consumption of circuit is main issue for every designer. This paper mainly dealing with the implementation of CMOS charge sharing latch comparator and analysis of it using different parameter in 90nm. For the implementation of new design the features of two important comparator are combined so that the power dissipation is reduced and speed of new design is increased. These two comparators are resistive dividing comparator and differential current sensing respectively. The simulation result is shown in 90nm technologies, for 2.4GHz clocked comparator by using 0.9V input.