Digital Circuit Architecture for a Median Filter of Grayscale Images Based on Sorting Network
In this paper, a digital circuit architecture dedicated to median filtering of grayscale images is presented. The architecture emerges from a sorting network based median algorithm which effectiveness is verified by Matlab programming and its hardware implementation tested on a Spartan-3E FPGA device. The median pixel computation is approached by a sorting network scheme which is constituted by seven three-data comparator modules and hierarchically composed by twenty one switch/compare circuits. The successful operation of the three data comparator module is demonstrated by transistor level SPICE simulations using 0.5 um CMOS technology.