International Journal of Engineering Research and Development (IJERD)
A digital clock frequency multiplier using floating point arithmetic, which generates the output clock with zero frequency error has been presented. The circuit has an unbounded multiplication factor range and low locks time. A low power mechanism has been incorporated to ensure that the overall power consumption of the circuit is less. The circuit has been designed in TSMC 65nm CMOS process for an input reference time of 0.01ns and has been verified with random multiplication factor values.