Digital Filter Design for CPT Atomic Clocks and FPGA Realization

Provided by: AICIT
Topic: Hardware
Format: PDF
The authors present their study result of applying digital filters in the Coherent Population Trapping (CPT) atomic clock. They design and realize the filter in a Field Programmable Gates Array (FPGA). The filter is constructed of a Cascaded Integrator-Comb (CIC) decimation filter, a CIC compensation filter, and a Finite-Impulse Response (FIR) filter in series. The CIC decimation filter operates for descending the sampling frequency and anti-aliasing, the CIC compensation filter refines the magnitude frequency response of the CIC decimation filter, and the FIR filter removes noises and extracts the wanted signal.

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