Provided by: Delft University of Technology
Date Added: Apr 2011
It is a well-known fact that modern computing is undergoing radical changes with respect to both the HardWare (HW) architecture and the approach to programming the plentiful of cores that modern HW increasingly contains. Even in the embedded domain, it is not uncommon anymore to find System-on-Chip (SoC) designs containing multiple, possibly heterogeneous cores connected together by a modern interconnect e.g., a Network-on-Chip (NoC) or a shared cache, optionally supporting performance guarantees per core/use cases. Many companies and various standardization bodies are working to ensure the success of this inherently parallel HW template.