George Washington University
Reconfigurable Computers (RCs) are gaining rising attention as an alternative to traditional processors for many applications. However, using RCs for operations with either large-size operands or large number of operands can be challenging given the bounded reconfigurable resources. In this paper, the authors propose a systematic methodology based on a Divide-and-Conquer technique for the implementation of such operations on RCs. A generic architecture is presented where schedulers are necessary to virtualize the usage of the limited resources. Two case studies, namely large-size-operand multiplication and large-number-of-operand FFT representing reduction and transformation operations respectively, were selected to demonstrate the effectiveness of the proposed approach. The experimental work was performed on one of the current RCs, i.e., SRC-6 reconfigurable computer.