Divide-and-Conquer Way Access for Low Power Mobile Caches

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Provided by: International Journal of Computer and Electrical Engineering (IJCEE)
Topic: Hardware
Format: PDF
As multi-core design concept is becoming dominant, power consumption of the shared level-2 caches is one of the critical issues along with its performance. This is more significant for mobile processors which are used in battery-powered devices. Designing a cache memory, increasing the cache size or adding more set-associatively is one of the simplest ways to improve the performance for both mobile processor and even general-purpose processors. In mobile processors, however, simple increase of the cache size can significantly affect the chip area and power consumption.
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