DRAM Power-Aware Rank Scheduling

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Provided by: Association for Computing Machinery
Topic: Storage
Format: PDF
Modern DRAMs provide multiple low-power states to save their energy consumption during idle times. The use of low-power states, however, can cause performance degradation because state transitions from low-power states to an active state incur time penalty. To effectively utilize the low-power states, the authors propose DRAM power-aware rank scheduling schemes applied to the last-level cache and the memory controller. Their scheme utilizing the last-level cache reduces write requests to DRAM and the state transitions by replacing cache blocks based on their dirty states and DRAM rank power states. Their scheme utilizing the memory controller decreases the state transitions with rank power state-aware batch writes.
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