DSTN (Distributed Sleep Transistor Network) for Low Power Programmable Logic Array Design
With the high demand of the portable electronic products, Low-power design of VLSI circuits & power dissipation has been recognized as a challenging technology in the recent years. PLA (Programming Logic Array) is one of the important off shelf part in the industrial application. This paper describes the new design of PLA using power gating structure sleep transistor at circuit level implementation for the low power applications. The important part of the power gating design i.e. header and footer switch selection is also describes in the paper. The simulating results of the proposed architecture of the new PLA is shown and compared with the conventional PLA.