Institute of Electrical & Electronic Engineers
To manage ever increasing complexity, advanced System-on-Chip (SoC) designs typically encompass a system integration process based on existing computation, storage and interconnect IPs. These IPs are designed separately, following a common interface, for example, AMBA, AXI, OCP-IP etc. Flow regulation is a traffic shaping technique, which can be used to achieve communication performance guarantees with low buffering cost when integrating IPs to Network-on-Chip (NoC) architectures. This paper presents dynamic flow regulation, which overcomes the rigidity of static flow regulation that pre-configures regulation parameters statically and only once.