Dynamic Hardware-Assisted Software-Controlled Page Placement to Manage Capacity Allocation and Sharing within Large Caches

Provided by: The University of Tulsa
Topic: Hardware
Format: PDF
In future multi-cores, large amounts of delay and power will be spent accessing data in large L2/L3 caches. It has been recently shown that OS-based page coloring allows Non-Uniform Cache Architecture (NUCA) to provide low latencies and not be hindered by complex data search mechanisms. In this paper, the authors extend that concept with mechanisms that dynamically move data within caches. The key innovation is the use of a shadow address space to allow hardware control of data placement in the L2 cache while being largely transparent to the user application and off-chip world.

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